1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing thereof, and more particularly, to a method of manufacturing a semiconductor device including an insulating layer with a contact hole.
2. Description of the Background Art
The demand of semiconductor devices is rapidly increasing in accordance with the significant spread of information equipment such as computers. Semiconductor devices having a large functional storage capacity and that is capable of operating at high speed are required. In response, technical development is in progress regarding increase in integration density, high speed response and reliability.
A semiconductor device having a multilayer structure where elements and interconnections are formed in a plurality of layers via interlayer insulating films is developed as means for increasing integration density of a semiconductor device. In such a semiconductor device having a multilayer structure, a small contact hole must be formed in the interlayer insulating film to obtain electrical contact between different layers. It has become necessary to form this contact hole in a small dimension and in high accuracy in a narrow space between adjacent elements to comply with the increased scale of integration of semiconductor devices.
The process of forming a contact hole of a memory cell array portion of a DRAM (Dynamic Random Access Memory) will be described hereinafter as an example of forming a conventional contact hole.
A DRAM will first be hereinafter.
FIG. 161 is a block diagram showing a structure of a general DRAM. Referring to FIG. 161, a DRAM 1350 includes a memory cell array 1351, a row and column address buffer 1352, a row decoder 1353, a column decoder 1354, a sense refresh amplifier 1355, a data-in buffer 1356, a data-out buffer 1357, and a clock generator 1358.
Memory cell array 1351 serves to store data signals of information. Row and column address buffer 1352 serves to receive an externally supplied address signal to select a memory cell forming a unitary storage circuit. Row decoder 1353 and column decoder 1354 serve to specify a memory cell by decoding an address signal. Sense refresh amplifier 1355 amplifies the signal stored in a specified memory cell to read out the same. Data-in buffer 1356 and data-out buffer 1357 serve to input or output data. Clock generator 1358 serves to generate a clock signal.
On a semiconductor chip of a DRAM of the above-described structure, memory cell array 1351 occupies a large area. Memory cell array 1351 has a plurality of memory cells arranged in a matrix for storing unitary storage information.
A memory cell forming memory cell array 1351 will be described hereinafter.
FIG. 162 is an equivalent circuit diagram of 4 bits of memory cells forming memory cell array 1351. Referring to FIG. 162, a memory cell includes one MOS transistor 1310 and one capacitor 1320 connected thereto. Transistor 1310 has its gate electrically connected to a word line 1307. Transistor 1310 has its source or drain electrically connected to a bit line 1317. The other of the source/drain of transistor 1310 is connected to capacitor 1320. This memory cell is a 1-transistor 1-capacitor type memory cell. A memory cell having such a structure facilitates increase of the integration density of a memory cell array due to its simple structure, and is widely used in DRAMs of large capacity.
Next, a conventional contact hole and a method of manufacturing thereof will be described hereinafter.
FIG. 163 is a plan view of a memory cell portion of a DRAM. Referring to FIG. 163, word lines (gate electrodes) 203a and 203b are arranged with a predetermined distance therebetween. A bit line 205 extends in a direction crossing word lines 203a and 203b. An element formation region 207 is formed to overlie bit line 205 and word lines 203a and 203b in an oblique manner. A storage node 209 forming the lower electrode of the capacitor is provided in element formation region 207. Storage node 209 is in direct contact with the semiconductor substrate (not shown) via a contact hole 211. Bit line 205 is in direct contact with the semiconductor substrate (not shown) via a contact hole 213.
FIG. 164 is a sectional view of the memory cell portion shown in FIG. 163 cut in the direction indicated by arrow A. Field oxide films 215 are spaced apart on semiconductor substrate 201. The main surface of silicon substrate 201 between field oxide films 215 is the element formation region 207. Impurity regions 217a, 217b, and 217c spaced apart are formed in element formation region 207. Gate electrodes 203a and 203b are formed above the main surface-of silicon substrate 201. A gate oxide film 219a is formed between gate electrode 203a and silicon substrate 201. A gate oxide film 219b is formed between gate electrode 203b and silicon substrate 201.
An insulating film 221 is formed to cover gate electrodes 203a and 203b. A TEOS (tetraethyl orthosilicate) film 223 is formed on silicon substrate 201 to cover insulating film 221. TEOS film 223 has a through hole 213 formed to expose impurity region 217b. A bit line 205 is formed on TEOS film 223. Bit line 205 is electrically connected to impurity region 217b via contact hole 213.
A method of manufacturing the structure shown in FIG. 163 will be described hereinafter. Referring to FIG. 165, field oxide film 215 for element isolation is formed at a predetermined area on the main surface of silicon substrate 201 using the LOCOS (Local Oxidation of Silicon) method. By forming a thin oxide film and then a polycrystalline silicon film on the main surface of silicon substrate 201 followed by a patterning process, gate electrodes 203a and 203b, and gate oxide films 219a and 219b are formed. Using gate electrodes 203a and 203b and field oxide film 215 as a mask, ions are implanted into silicon substrate 201 to form impurity regions 217a-217c of relatively low concentration. Insulating film 221 is formed to cover gate electrodes 203a and 203b. By carrying out ion implantation using insulating film 221 as a mask, impurity regions 217a, 217b, and 217c of relatively high concentration are formed. As a result, impurity regions 217a, 217b, and 217c having a LDD structure are obtained.
As shown in FIG. 166, TEOS film 223 is formed all over the main surface of silicon substrate 201. A stepped portion is generated reflecting the underlying configuration at the surface 223a of TEOS film 223. If a bit line is formed thereabove, it may be disconnected due to the generated stepped portion. A planarization process which will be described hereinafter is carried out to prevent such a problem.
Referring to FIG. 167, a SOG (Spin-On Glass) film 225 is formed on TEOS film 223. SOG film 225 has a low viscosity. Therefore, the surface 223a of SOG film 225 is planarized.
Referring to FIG. 168, the layer of SOG film 225 and TEOS film 223 is etched back, so that the surface 223a of TEOS film 223 is planarized.
Referring to FIG. 169, a resist 227 is formed on TEOS film 223. Resist 227 is exposed and developed to form an opening 227a in resist 227.
Referring to FIG. 170, TEOS film 223 is selectively removed by etching using resist 227 as a mask to form a contact hole 213 reaching to impurity region 217b. Then, resist 227 is removed. As shown in FIG. 164, bit line 205 is formed on TEOS film 223.
Next, a structure and a manufacturing method of a memory cell in a DRAM to which a conventional contact hole and a manufacturing method thereof is applied will be described hereinafter as conventional first, second and third semiconductor memory devices.
FIG. 171 is a sectional view of a first conventional semiconductor memory device having a stacked capacitor. Referring to FIG. 171, a memory cell includes one transfer gate transistor 1010 and one capacitor 1420.
Transfer gate transistor 1010 includes a pair of source/drain diffusion regions 1009, a gate oxide film 1005, and a gate electrode 1007. The pair of source/drain diffusion regions 1009 are formed with a distance therebetween in a region isolated by an isolation oxide film 1003 in a silicon substrate 1001. Source/drain diffusion region 1009 has a LDD (Lightly Doped Drain) structure of a double layer including an impurity region 1009a of a relatively low concentration and an impurity region 1009b of a relatively high concentration. A gate electrode (word line) 1007 is formed on the region sandwiched by the pair of source/drain diffusion regions 1009 with gate oxide film 1005 thereunder. An insulating film 1011 of silicon oxide (SiO2) is formed on the surface of gate electrode 1007. A sidewall 1013 is formed to cover the sidewalls of gate electrode 1007 and insulating film 1011.
A thin silicon oxide film 1015 is formed all over the surface of silicon substrate 1001 so as to cover transfer gate transistor 1010. A contact hole 1015a is formed in this thin silicon oxide film 1015. A partial surface of either the source or drain diffusion region 1009 is exposed in contact hole 1015a. A buried bit line 1017 is formed to contact source/drain diffusion region 1009 via contact hole 1015a. An interlayer insulating film 1019 of a thickness of approximately 8000 xc3x85 is formed all over the surface of silicon substrate 1001 so as to cover buried bit line 1017. A silicon nitride film (Si3N4) 1021 of a thickness of approximately 100 xc3x85 is formed on the surface of interlayer insulating film 1019. A contact hole 1435 is formed to penetrate the three layers of silicon nitride film 1021, interlayer insulating film 1019, and silicon oxide film 1015. A partial surface of the other source/drain diffusion region 1009 is exposed in contact hole 1435. A capacitor 1420 is formed to be in electrical contact with source/drain diffusion region 1009 via contact hole 1435.
Capacitor 1420 includes a lower electrode layer (storage node) 1423, a capacitor dielectric film 1425, and an upper electrode layer (cell plate) 1427. Lower electrode layer 1423 is formed of polycrystalline silicon. Lower electrode layer 1423 is formed on the surface of silicon nitride film 1021 to contact source/drain diffusion region 1009 via contact hole 1435. Capacitor dielectric film 1425 is formed to cover the surface of lower electrode layer 1423. Upper electrode 1427 of polycrystalline silicon (poly-Si) is formed to cover the surface of lower electrode layer 1423 with capacitor dielectric film 1425 therebetween. Insulating film 1429 is formed to cover capacitor 1420.
A method of manufacturing the first conventional semiconductor memory device shown in FIG. 171 will be described hereinafter.
FIGS. 172-184 are sectional views of the first conventional semiconductor memory device showing the sequential manufacturing steps thereof.
Referring to FIG. 172, an isolation oxide film 1003 is formed on a silicon substrate 1001. A silicon oxide film 1005 which becomes a gate oxide film is formed all over the surface of silicon substrate 1001 by thermal oxidation and the like. A polycrystalline silicon film 1007 and then a silicon oxide film 1011 is formed all over the surface of silicon substrate 1001 by a CVD method (Chemical Vapor Deposition). A photoresist is applied all over the surface of silicon oxide film 1011 to be patterned to a predetermined configuration by exposure to result in a resist pattern 1433a. Using resist pattern 1443a as a mask, silicon oxide film 1011 and then polycrystalline silicon film 1007 are sequentially etched away.
Referring to FIG. 173, a gate electrode 1007 of polycrystalline silicon is formed in a desired configuration by this etching process. Using gate electrode 1007, insulating film 1011, and isolation oxide film 1003 as a mask, ions are implanted into the surface of silicon substrate 1001. By this ion implantation, an impurity region 1009a of relatively low concentration is formed on the surface of silicon substrate 1001 below the lower region of gate electrode 1007.
Referring to FIG. 174, a silicon oxide film 1013 substantially uniform in thickness is formed all over the surface of silicon substrate 1001 to cover gate electrode 1007 and insulating film 1011. Then, anisotropic etching is applied to silicon oxide film 1013.
Referring to FIG. 175, a sidewall 1013 is formed to cover the sidewalls of gate electrode 1007 and insulating film 1011 by this anisotropic etching process. Then, ions are implanted into the surface of silicon substrate 1001 using gate electrode 1007, insulating film 1011, sidewall 1013 and isolation oxide film 1003 as a mask. By this ion implantation, an impurity region 1009b of a relatively high concentration is formed on silicon substrate 1001 in contact with impurity region 1009a of a relatively low concentration. Thus, a source/drain diffusion region 1009 of a LDD structure is formed by these impurity regions 1009a and 1009b of relatively low and high concentration, respectively. This pair of source/drain diffusion regions 1009, gate oxide film 1005, and gate electrode 1007 form transfer gate transistor 1010.
Referring to FIG. 176, a thin silicon oxide film 1015 is formed all over the surface of silicon substrate 1001 so as to cover transfer gate transistor 1010. A photoresist is applied all over the surface of silicon oxide film 1015 to be subjected to an exposure process of patterning to a desired configuration. .This results in resist pattern 1433b. Using resist pattern 1433b as a mask, silicon oxide film 1015 is etched.
Referring to FIG. 177, a contact hole 1015a is formed by this etching step in silicon oxide film 1015 to expose the surface of one of the pair of source/drain diffusion regions 1009. A polycrystalline silicon film 1017 is formed on the surface of silicon oxide film 1015 to come into contact with source/drain diffusion region 1009 via contact hole 1015a. A silicon oxide film 1019a is formed on the surface of polycrystalline silicon film 1017.
Referring to FIG. 178, silicon oxide film 1019a and then polycrystalline silicon film 1017 are etched by photolithography, RIE (Reactive Ion Etching) or the like. By this etching process, a buried bit line 1017 electrically in contact with source/drain region 1009 is formed via contact hole 1015a. 
Referring to FIG. 179, a silicon oxide film 1019b is formed all over silicon substrate 1001 by CVD. A resist film 1019c having its surface planarized is formed on the surface of silicon oxide film 1019b. This resist film 1019c may be formed by applying a SOG (Spin On Glass) film. Then, resist film 1019c and silicon oxide film 1019b are etched back to a level indicated by the broken line in FIG. 179.
Referring to FIG. 180, an interlayer insulating film 1019 having its surface substantially planarized is obtained by this etchback process. A silicon nitride film 1021 of approximately 100 xc3x85 in thickness is formed on the surface of interlayer insulating film 1019.
Referring to FIG. 181, a photoresist is applied all over the surface of silicon nitride film 1021 to be subjected to an exposure process to be patterned to a desired configuration. As a result, a resist pattern 1433c is formed. Using resist pattern 1433c as a mask, silicon nitride film 1021, interlayer insulating film 1019, and silicon oxide film 1015 are etched anisotropically in a sequential manner. As a result, a contact hole 1435 exposing the surface of either the source or drain diffusion region is formed. Then, resist pattern 1433c is removed.
Referring to FIG. 182, a polycrystalline silicon film 1423 is formed on the surface of silicon nitride film 1021 to come in contact with source/drain diffusion region 1009 via contact hole 1435.
Referring to FIG. 183, polycrystalline silicon film 1423 is patterned to a desired configuration by photolithography, RIE or the like, whereby a lower electrode layer 1423 electrically connected to source/drain diffusion region 1009 is formed.
Referring to FIG. 184, a capacitor dielectric film 1425 is formed so as to cover the surface of lower electrode layer 1423. An upper electrode layer 1427 of polycrystalline silicon is formed to cover lower electrode layer 1423 with capacitor dielectric film 1425 therebetween. Lower electrode layer 1423, capacitor dielectric film 1425, and upper electrode layer 1427 form capacitor 1420. An insulating film 1429 is formed to cover capacitor 1420.
A second conventional semiconductor memory device will be described hereinafter.
FIG. 185 is a sectional view of a second conventional semiconductor memory device. Referring to FIG. 185, the structure of the second conventional semiconductor memory device differs from the first conventional semiconductor memory device in the structure of its capacitor.
Capacitor 1420 of the second conventional semiconductor memory device includes a lower electrode layer 1423, a capacitor dielectric film 1425, and an upper electrode layer 1427. Lower electrode layer 1423 is formed of polycrystalline silicon. Lower electrode layer 1423 includes an extending region 1423a and a cylindrical portion 1423b. Extending portion 1423a is formed on the surface of silicon nitride film 1021 to come in contact with source/drain diffusion region 1009 via a contact hole 1435 piercing silicon nitride film 1021, interlayer insulating film 1019 and silicon oxide film 1015 and reaching to the surface of source/drain diffusion region 1009. Cylindrical portion 1423b is formed to grow upwards perpendicular to the surface of silicon substrate 1001 and having its bottom in contact with the outer peripheral portion of extending portion 1423a. A capacitor dielectric film 1425 is formed to cover the surface of lower electrode layer 1423. An upper electrode layer 1427 of polycrystalline silicon is formed to cover the source of lower electrode layer 1423 with capacitor dielectric film 1425 therebetween.
The structures of the elements other than capacitor 1420 of the second conventional semiconductor memory device are substantially similar to those of the first conventional semiconductor memory device, and their description will not be repeated.
The manufacturing method of the second conventional semiconductor memory device having the above-described cylindrical type stacked capacitor will be described hereinafter.
FIGS. 186-191 are sectional views of the second conventional semiconductor memory device showing the manufacturing steps thereof. The process preceding the step shown in FIG. 186 of the second conventional semiconductor memory device is similar to the manufacturing steps of the first conventional semi-conductor memory device, and their description will not be repeated.
Referring to FIG. 187, an insulating film 1431 is formed all over the surface of polycrystalline silicon film 1423a. Insulating film 1431 is patterned to a desired configuration by photolithography, RIE or the like. Using this patterned insulating film 1431 as a mask, polycrystalline silicon film 1423a is etched. As a result, an extending portion 1423a electrically connected to the source/drain diffusion region 1009 via contact hole 1435 is formed.
Referring to FIG. 188, a polycrystalline silicon film 1423b is formed all over silicon substrate 1001 so as to cover the remaining insulating film 1431 and extending portion 1423a. Polycrystalline silicon film 1423b is subjected to anisotropic etching until the surface of silicon nitride film 1021 is exposed.
Referring to FIG. 189, a sidewall spacer-like cylindrical portion 1423b is formed by this anisotropic etching process to cover the sidewall of insulating film 1431. Cylindrical portion 1423b has its bottom end in contact with the outer periphery of extending portion 1423a. 
Then, insulating film 1431 filling the inside region of cylindrical portion 1423b is removed by etching. At this etching process, silicon nitride film 1021 serves to protect the surface of interlayer insulating film 1019.
Referring to FIG. 190, an lower electrode layer 1423 of extending portion 1423a and silicon portion 1423b is formed by this etching process.
Referring to FIG. 191, a capacitor dielectric film 1425 is formed to cover the surface of lower electrode layer 1423. An upper electrode layer 1427 of polycrystalline silicon is formed to cover the surface of lower electrode layer 1423 with capacitor dielectric film 1425 therebetween. Thus, a capacitor 1420 including lower electrode layer 1423, capacitor dielectric film 1425, and upper electrode layer 1427 is formed. Then, an insulating film 1429 is formed to cover capacitor 1420 to result in the structure shown in FIG. 185.
Such a cylindrical stacked type capacitor is disclosed in, for example, Japanese Patent Laying-Open No. 62-286270, Japanese Patent Laying-Open No.1-257365, and xe2x80x9cVL Symposiumxe2x80x9d 1989, pp. 69 and 70.
A third conventional semiconductor memory device having a fin type stacked capacitor will be described hereinafter.
FIG. 192 is a sectional view of the third conventional semiconductor memory device. Referring to FIG. 192, a memory cell is formed in a region isolated by an isolation oxide film 1503 on a silicon substrate 1501. This memory cell includes a transfer gate transistor 1510 and a capacitor 1520.
Transfer gate transistor 1510 includes a pair of source/drain diffusion regions 1509, a gate oxide film 1505, and a gate electrode 1507. The pair of source/drain diffusion regions 1509 are formed on the surface of silicon substrate 1501 with a predetermined distance therebetween. A gate electrode (word line) 1507 is formed on a region sandwiched by the pair of source/drain diffusion regions 1509 with a gate oxide film 1505 thereunder. An interconnection layer 1507 serving as a word line is formed on the surface of isolation oxide film 1503.
An insulating film 1511 is formed all over the surface of silicon substrate 1501 so as to cover transfer gate transistor 1510 and interconnection layer 1507. A contact hole 1511a is formed in insulating film 1511. A partial surface of one of the source/drain diffusion regions 1509 is exposed in contact hole 1511a. A buried bit line 1513 is formed on the surface of insulating film 1511 to come in contact with source/drain diffusion region 1509 via contact hole 1511a. 
A silicon nitride film (SiN) 1515 is formed to cover buried bit line 1513. A contact hole 1535 is formed to penetrate the two layers of silicon nitride film 1515 and insulating film 1511. A partial surface of the other of the source/drain diffusion regions 1509 is exposed in contact hole 1535. A capacitor 1520 is formed via contact hole 1535 to come in electrical contact with source/drain diffusion region 1509.
Capacitor 1520 includes a lower electrode layer 1521, a capacitor dielectric film 1523, and an upper electrode layer 1525. Lower electrode layer 1521 includes a first portion 1521a and a second portion 1521b of polycrystalline silicon. Lower electrode layer 1521 has a fin structure. More specifically, the first and second portions 1521a and 1521b formed above silicon nitride film 1515 have a layered structure with a predetermined distance therebetween. The second portion 1521b contacts the first portion 1521a and also source/drain diffusion region 1509 via contact hole 1531. The first and second portions 1521a and 1521b have a configuration according to the surface configuration of the underlying silicon nitride film 1515. A capacitor dielectric film 1523 is formed to cover the surface of lower electrode layer 1521. Upper electrode layer 1525 is formed to cover the surface of lower electrode layer 1521 with capacitor dielectric film 1523 therebetween.
A method of manufacturing the third conventional semiconductor memory device will be described hereinafter.
FIGS. 193-198 are sectional views of the third conventional semiconductor memory device showing the manufacturing steps thereof. Referring to FIG. 193, an isolation oxide film 1503 is formed on the surface of a silicon substrate 1501. A thin silicon oxide film 1505 which becomes a gate oxide film is formed all over the surface of silicon substrate 1501. A gate electrode (word line) 1507 patterned to a predetermined shape is formed on the surface of silicon oxide film 1505. By ion implantation using gate electrode 1507 and isolation oxide film 1503 as a mask, source/drain diffusion region 1509 is formed on the surface of silicon substrate 1501 so as to sandwich the lower region of gate electrode 1507. Thus, transistor 1510 is formed.
Referring to FIG. 194, an insulating film 1511 is formed to cover gate electrode 1507. A contact hole 511a exposing a partial surface of one of the source/drain diffusion regions 1509 is formed penetrating the two layers of insulating film 1511 and silicon oxide film 1505. A buried bit line 1513 is formed on the surface of insulating film 1511 to contact source/drain diffusion region 1509 via contact hole 1511a. 
Referring to FIG. 195, a silicon nitride film 1515 is formed all over the surface of silicon substrate 1501 to cover-buried bit line 1513. A silicon oxide film 1531, a first polycrystalline silicon film 1521a, and a silicon oxide film 1533 substantially uniform in thickness are sequentially formed on the surface of silicon nitride film 1515. Then, a contact hole 1535 exposing the surface of the other source/drain diffusion region 1509 is formed by photolithography and RIE, penetrating silicon-oxide film 1533, first polycrystalline silicon film 1521a, silicon oxide film 1531, silicon nitride film 1515, insulating film 1511 and silicon oxide film 1505.
Referring to FIG. 196, a second polycrystalline silicon film 1521b is formed all over the surface of silicon oxide film 1533 to come in contact with source/drain diffusion region 1509 via contact hole 1535. Second polycrystalline silicon film 1521b, silicon oxide film 1533, and then first polycrystalline silicon film 1521a are etched away sequentially by photolithography, RIE, and the like. By this etching process, first and second portions 1521a and 1521b implementing lower electrode layer 1521 are formed from the first and second polycrystalline silicon films 1521a and 1521b. Lower electrode layer 1521 is formed to be in electrical contact with source/drain diffusion region 1509 via contact hole 1535. Then, by a fluoric (HF) acid agent process, silicon oxide films 1531 and 1533 are removed to result in the structure shown in FIG. 197.
Referring to FIG. 198, a capacitor dielectric film 1523 is formed to cover the surface of lower electrode layer 1521. An upper electrode layer 1525 is formed to cover lower electrode layer 1521 with capacitor dielectric film 1523 therebetween. Thus, a capacitor 1520 is formed by lower electrode layer 1521, capacitor dielectric film 1523, and upper electrode layer 1525.
Such a fin type stacked capacitor is disclosed in IEDM 88, pp. 592-595 by T. Ema et al.
A conventional contact hole and a method of manufacturing thereof have the problems set forth in the following.
To comply with increase in the integration density of a DRAM, miniaturization is also required in the memory cell portion. More specifically, a memory cell having a pitch of 1.3 xcexcm between word lines (gate electrodes) 203a and 203b is now considered, as shown in FIG. 199. In such a memory cell having a pitch of 1.3 xcexcm, the distance between word lines 203a and 203b will be 0.8 xcexcm if the width of word line 203a is 0.5 xcexcm. The minimum size of opening 227a in resist 227 (refer to FIG. 169) is 0.5 xcexcm from the current limitation of photolithographic technique. Under such a limitation, the distance between contact hole 213 and word line 203a or 203b is 0.15 xcexcm. This means that the distance of 0.15 xcexcm between contact hole 213 and word line 203a or 203b becomes the overlay margin between bit line 205 and word line 203a or 203b. 
The overlay accuracy of photolithography is currently approximately 0.18 xcexcm in the level of mass production. This means that contact hole 213 may be formed overlying word line 203a or 203b under the current overlay accuracy. In such a case, shorting will occur between bit line 205 and word line 203a or 203b. 
FIG. 200 and FIGS. 201-203 are a plan view and sectional views, respectively, for describing the problems encountered in forming a memory cell of a 1.3 xcexcm pitch. As shown in FIG. 200, there is a possibility of opening 227a in resist 227 (refer to FIG. 169) being shifted 0.13 xcexcm horizontally from the center of alignment taking into consideration the current overlay accuracy of photolithography, resulting in opening 227a and word line 203a partially overlapping with each other.
FIG. 201 is a sectional view of FIG. 200 taken along line B. By etching anisotropically TEOS film 223 using resist 227 as a mask under the state of FIG. 201, the side of word line (gate electrode) 203a will be exposed as shown in FIG. 202. If bit line 205 is formed after removal of resist 227, shorting occurs between bit line 205 and word line 203a as shown in FIG. 203. That is to say, there was problem of shorting between a bit line and a word line in a conventional contact hole and a method of manufacturing thereof.
A method of providing a contact hole having an opening diameter smaller than the minimum dimension that can be formed by photolithography is disclosed in Japanese Patent Laying-Open No. 62-86715. This technique will be described with reference to FIGS. 204-207. Referring to FIG. 204, an impurity region 233 is formed on the main surface of a semiconductor substrate 231. An interlayer insulating film 235 is formed on semiconductor substrate 231 to cover impurity region 233. A resist 237 is formed on interlayer insulating film 235. The opening diameter of an opening 237a of resist 237 is of the minimum dimension that can be formed by the current photolithography technique. Interlayer insulating film 235 is selectively etched using resist 237 as a mask, whereby this etching process is stopped just before reaching to impurity region 233. Thus, a first hole 239 is formed in interlayer insulating film 235.
Referring to FIG. 205, resist 237 is removed and a polycrystalline silicon film 241 is formed all over.
Referring to FIG. 206, overall etching is carried out on polycrystalline silicon film 241 to form a sidewall layer 241a of polycrystalline silicon at the sidewall of first hole 239. Then, a resist 245 is formed all over. Interlayer insulating film 235 is selectively etched using resist 245 and sidewall layer 241a as a mask to form a second hole (contact hole) 243 exposing impurity region 233. Because sidewall layer 241a is used as a mask, the opening diameter of contact hole 243 is smaller than the minimum dimension that can be formed by photolithography.
Referring to FIG. 207, the surface of sidewall layer 241a is oxidized to form an oxide film 247. Then, an aluminum film 249 is formed all over the surface. Aluminum film 249 is electrically connected to impurity region 233 via contact hole 243.
The above-described technique has problems set forth in the following. There is a possibility of an uneven surface of the polycrystalline silicon film due to grain boundary. FIG. 208 shows the case where polycrystalline silicon film 241 is formed on interlayer insulating film 235. There is a convex portion 241b due to crystalline grain boundary in polycrystalline silicon film 241. An overall etching of polycrystalline silicon film 241 with convex portion 241b generated at the sidewall of first hole 239 will result in the configuration shown in FIG. 209.
Referring to FIG. 209, the dotted line inside sidewall layer 241a of the right side indicates the surface of sidewall layer 241a when there is no convex portion 241b. The dimension of the opening defined by the right sidewall layer 241a and the left sidewall layer 241a are indicated by L1 and L2. L1 and L2 indicate the cases where convex portion 241b is not present or present, respectively, in polycrystalline silicon film 241. It can be appreciated that the dimension of the opening defined by the right sidewall layer 241a and the left sidewall layer 241a varies depending on the unevenness of the surface of polycrystalline silicon film 241. This means that the opening diameter of the contact hole formed using this as a mask will not be constant. Therefore, a contact hole cannot be manufactured with superior controllability of the opening diameter.
The above-described first, second and third conventional semiconductor memory devices have problems set forth in the following.
When the integration density of a DRAM is to be increased, reduction in the size of a memory cell is inevitable. In accordance with reduction of the memory cell size, the pitch between word lines is also reduced. Those having a dimension LO of 0.6 xcexcm between word lines (gate electrodes) 1007 shown in FIG. 171 are now under study. The opening diameter Lc of a contact hole 1435 is limited to 0.4 xcexcm from the standpoint of the photolithography technique. (It is to be noted that this condition is based on a design rule differing from that of the above-described problems of a conventional contact hole and a manufacturing method thereof.) Under such circumstances, the dimension LD between contact hole 1435 and word line 1007 is 0.1 xcexcm. This means that the dimension LD of 0.1 xcexcm between word line 1007 and contact hole 1435 is the overlay margin of a mask at the time of formation of a contact hole 1435.
However, the overlay accuracy of a mask by photolithography is approximately 0.18 xcexcm under mass production. Therefore, there is a possibility of lower electrode layer 1423 and word line 1007 coming into contact with each other under the condition of the above-described overlay margin. This problem will be described in details hereinafter.
FIGS. 210-212 are sectional views of a structure where a lower electrode layer and a word line are formed in contact with each other, showing the manufacturing steps thereof. Referring to FIG. 210, first a resist pattern 1433c is formed on silicon nitride film 1021 in forming a contact hole in interlayer insulating film 1019 reaching source/drain diffusion region 1009. During this formation step, the center of a hole pattern 1434 of resist pattern 1433c (the chain dotted line Qxe2x80x94Q) may be offset within the range of 0.18 xcexcm leftwards or rightwards from the alignment center (the chain dotted line Pxe2x80x94P) to result in the offset of LE. An offset of LE exceeding the overlay margin of 0.1 xcexcm will result in the structure shown in FIG. 211. More specifically, when silicon nitride film 1021, interlayer insulating film 1019, silicon oxide film 1015 are etched anisotropically using resist pattern 1433 having an offset LE exceeding 0.1 xcexcm, the side face of word line 1007 will be exposed from the sidewall of contact hole 1435a. If resist pattern 1433c is then removed to form capacitor 1420 under such a state, shorting will occur between lower electrode layer 1423 and word line 1007 as shown in FIG. 212.
Thus, there is a problem that shorting will occur between one electrode of the capacitor and a word line when the memory cell size is reduced in response to increasing the integration density of a DRAM.
In general, the capacitance of a capacitor is proportional to the opposing area of the electrodes, and is inversely proportional to the thickness of the capacitor dielectric film. Therefore, it is desired to increase the opposing area between electrodes in a capacitor from the standpoint of increasing the capacitor capacitance. In contrast, the memory cell size must be reduced if the integration density is to be increased in a DRAM. In response to reduction of the memory cell size, the planar occupying area of a capacitor is accordingly reduced.
Referring to FIG. 171 showing the capacitor structure of the first conventional semiconductor memory device, the surface region of lower electrode layer 1423 opposing upper electrode layer 1427 has a relatively planarized surface. Lower electrode layer 1423 has a configuration that extends horizontally. Therefore, the surface area of lower electrode layer 1423 is reduced substantially in proportion to the reduction of the planar occupying area, resulting in reduction of the opposing area of electrodes in a capacitor. This means that the charge amount stored in a capacitor (the charge amount stored in a 1-bit memory cell) is reduced. If the charge amount stored in a memory cell of 1 bit becomes lower then a predetermined value, the operation of the DRAM as a storage region becomes unsteady to degrade its reliability.
Referring to FIG. 185 showing the capacitor structure of the second conventional semiconductor memory device, lower electrode layer 1423 has a cylindrical portion 1423b extending upwards perpendicular to the surface of the semiconductor substrate. The surface area of cylindrical portion 1423b shows almost no reduction even when the planar occupying area is reduced. This means that the capacitance of the capacitor can be ensured by controlling the height of cylindrical portion 1423b even when the size of the memory cell is reduced in accordance with increase in integration density. However, if the height of the cylindrical portion 1423b is increased, the stepped difference between the memory cell region and the peripheral circuit region will be increased. Therefore, the pattern formation of an interconnection layer extending over two regions is degraded due to restriction of the depth of focus of an exposure apparatus. This means that the height of a cylindrical portion 1423b is limited, resulting in limitation of the capacitance of a capacitor 1420. In the case of further increasing the integration density, the charge amount stored in a memory cell of 1 bit will become lower than a predetermined value, whereby the DRAM serving as a storage region will show unsteady operation, as in the case of the above-described cylindrical capacitor structure.
Thus, there was a problem that reliability is deteriorated when the size of a memory cell is reduced in response to increase in integration density with unsteady operation of the DRAM.
The problem of the third conventional semiconductor memory device will be described hereinafter.
Referring to FIG. 195, a first polycrystalline silicon film 1521a which becomes a portion of the lower electrode layer is formed on the surface of silicon oxide film 1531. There is a stepped portion at the surface of silicon oxide film 1531 reflecting the stepped portion of the underlying layer. Therefore, when first polycrystalline silicon film 1521a is subjected to anisotropic etching as shown in FIG. 196, residue of silicon oxide film 1521a remains along the sidewall portion at the stepped portion of the surface of silicon oxide film 1531, resulting in the structure shown in FIGS. 213A and 213B.
FIG. 213A is a plan view schematically showing the structure where residue is left at the stepped portion at the surface of silicon oxide film 1531. FIG. 213B is a sectional view taken along line Rxe2x80x94R of FIG. 213A. Referring to FIGS. 213A and 213B, the etching residues 1522a and 1522b of polycrystalline silicon film 1521a are seen along the sidewall of the stepped portion of silicon oxide film 1531. It is to be noted that residue 1522a forms a contact with capacitor 1020.
Then, a fluoric acid process is carried out to etch away silicon oxide films 1531 and 1533. Because this etching is carried out in an isotropical manner, silicon oxide film 1531 underlying residues 1522a and 1522b are completely removed. This complete removal of silicon oxide film 1531 will cause residue 1522b to be detached from the silicon substrate. However, residue 1522a remains in a state bridging capacitor 1020 even when the underlying layer is removed. Thus, a plurality of capacitors 1020 will be left in an electrically connected manner due to residue 1522a. There is also the possibility of residue 1522b detached from the semiconductor substrate and floating in the fluoric acid agent to be reattached to the semiconductor substrate to form electrical connection between the plurality of capacitors. If a plurality of capacitors 1020 are left in an electrically connected manner, the storing and erasing operation of data by charge storage of a capacitor can not be selectively carried out between memory cells.
An object of the present invention is to provide a semiconductor device having a contact hole of an opening diameter smaller than the minimum dimension that can be formed by photolithography technique, and a manufacturing method thereof.
Another object of the present invention is to provide a semiconductor device having a contact hole formed with superior control of the opening diameter, and a method of manufacturing thereof.
A further object of the present invention is to provide a semiconductor memory device that can have shorting between one electrode of a capacitor and a word line prevented even if the memory cell size is reduced according to increase in integration density, and a method of manufacturing thereof.
Still another object of the present invention is to provide a semiconductor memory device that has stable operation of a DRAM to improve reliability even when the memory cell size is reduced according to increase in integration density, and a method of manufacturing thereof.
A still further object of the present invention is to provide a semiconductor memory device that has shorting between capacitors prevented for reliable selective recording and erasing operation of data between each memory cell.
According to an aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of: forming a first film on a semiconductor substrate, forming on the first film an etching mask having an opening exposing a partial surface of the first film, forming a first hole having a sidewall and a bottom wall of the first film by selectively etching the first film using the etching mask, removing the etching mask, forming a second hole having a sidewall and a bottom wall of the second film and a diameter smaller than that of the first hole by forming a second film of a material having an under-etching characteristic identical to that of the first film on the first film including the sidewall and the bottom of the first hole, and forming a third hole having a sidewall matching the sidewall of the second hole by etching anisotropically the first and second films.
According to a preferable aspect of manufacturing a semiconductor device of the present invention, anisotropic etching of the first and second films are carried out using gas having CO gas added to CF type gas.
In the method of manufacturing a semiconductor device according to the one aspect of the present invention, the first film is selectively etched using the etching mask. By this etching, the first hole having a sidewall and a bottom wall of the first film is formed. By forming on the first film including the sidewall and the bottom wall of the first hole a second film of a material having an under-etching characteristic equal to that of the first film, a second hole having a sidewall and a bottom wall of the second film and a diameter smaller than that of the first hole is formed. By etching anisotropically the first and second films, a third hole having a sidewall matching the sidewall of the second hole can be formed. Because the sidewall of the third hole matches the sidewall of the second hole, the diameter of the third hole becomes smaller than that of the first hole. Therefore, when the diameter of the first hole is that of the minimum dimension that can be formed by photolithography, the diameter of the third hole becomes smaller than that of the minimum dimension that can be formed by photolithography. Also, the upper layer portion of the sidewall of the third hole has a smooth inclination because an etching mask is not used in forming the third hole.
According to another aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of: forming a first film on a semiconductor substrate, forming on the first film an etching mask having an opening exposing a partial surface of the first film, forming a first hole having a sidewall and a bottom wall of the first film and a diameter reduced towards the semiconductor substrate by etching the first film selectively and anisotropically using the etching mask, removing the etching mask, and forming a second hole having a sidewall matching the sidewall of the first hole by etching anisotropically the first film.
In a method of manufacturing a semiconductor device according to the another aspect of the present invention, a first film is etched selectively using an etching mask. By this etching, a first hole having a sidewall and a bottom wall of the first film and a diameter that becomes smaller towards the semiconductor substrate is formed. More specifically, this etching results in tapering of the sidewall of the hole. Therefore, when the diameter of the opening in the etching mask is set to the minimum dimension that can be formed by photolithography, the diameter of the lower end portion of the first hole can be made smaller than the minimum dimension that can be formed by photolithography. Following the formation of the first hole, the etching mask is removed. Then, by etching anisotropically the first film, a second hole having a sidewall matching the sidewall of the first hole is formed. Because the diameter of the lower portion of the first hole can be made smaller than the minimum dimension that can be formed by photolithography, the diameter of the second hole can also be made smaller than the minimum dimension that can be formed by photolithography. Also, the upper portion of the sidewall of the second hole can take a smooth inclination because an etching mask is not used in the formation of the second hole.
The etching mask is removed after formation of the first hole to avoid the possibility of the etching inhibited due to the lower end portion of the first hole being filled with the material of the etching mask as a result of reduction in the diameter of the first hole.
According to a preferable aspect of manufacturing a semiconductor device of the present invention, anisotropic etching for forming the second hole is carried out using gas in which CO gas is added to CF type gas.
According to a further aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of: forming an insulating film in contact with the main surface of a semiconductor substrate, forming a first film on the insulating film of a material different from the under-etching characteristics of the insulating film, forming on the first film a second film of a material different from the under-etching characteristic of the first film, forming a first hole having a sidewall of the second film by selectively etching the second film to expose the surface of the first film, forming on the second film including the sidewall of the first hole a third film of a material different from the under-etching characteristic of the second film, forming a sidewall layer at the sidewall of the first hole by etching anisotropically the third film, forming a second hole exposing the surface of the insulating film and having a diameter smaller than that of the first hole by etching anisotropically the first film using the second film and the sidewall layer as a mask, and forming in the insulating film a third hole communicating with the second hole and reaching the main surface of the semiconductor substrate by etching anisotropically the insulating film using the first film as a mask.
According to a preferable method of manufacturing a semiconductor device of the present invention, the first film is selected from the group consisting of polycrystalline silicon, silicide, and refractory metal.
The semiconductor device of the present invention includes a semiconductor substrate having a main surface, a conductive region formed at the main surface of the semiconductor substrate, an insulating film formed on the conductive region and having a hole reaching to the conductive region, and an interconnection film formed on the insulating film and connected to the conductive region via the hole, wherein the hole formed in the insulating film has an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique, and the interconnection film has a portion extending in the direction along the upper face of the insulating film. This extending portion has at least two layers extending in that direction.
In a method of manufacturing a semiconductor device according to the further aspect of the present invention, a second hole is formed in the first film using the sidewall layer formed on the sidewall of the first hole and the second film as a mask, followed by the etching of the insulating film anisotropically using the first film as a mask. Therefore, the third hole can easily be formed in self-alignment that is smaller by the width of the sidewall layer than the minimum dimension that can be formed by photolithography. Thus, a hole can be formed in a smaller space by the same design rule, and the overlay margin can be increased in patterning by photolithography.
According to an aspect of a semiconductor device of the present invention formed by the above-described manufacturing method, the hole formed in the insulating film has an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique. Therefore, even when a hole is provided between interconnection layers provided on the same layer with a predetermined distance therebetween, the overlay margin between the hole and the interconnection layer is increased by the reduced dimension of the opening diameter. Therefore, the pitch between the interconnection layers can be reduced to improve the integration density.
According to still another aspect of the present invention, a method of manufacturing a semiconductor device, in addition to the step of forming the third hole, includes the steps of: forming a resist on the first film so as to fill the third hole with the resist after formation of the third holes exposing the first film by etching the resist and leaving the resist in the third hole, removing the second film by etching using the resist filled in the third hole as a mask, and removing the resist.
In a method of manufacturing a semiconductor device according to the still another aspect of the present invention, the first film is removed by etching using the resist filled in the third hole as a mask. Therefore, the stepped portion can be reduced in the film formed on the insulating film at a subsequent process. Because the third hole is filled with a resist, an underlying interconnection layer if present below the third hole will not be damaged.
According to a still further aspect of the present invention, a method of manufacturing a semiconductor device includes the steps of, after the formation of the third hole, forming a conductive film on the first film so that the third hole is filled with the conductive film, exposing the insulating film by etching the conductive film and the first film leaving the conductive film in the third hole, and forming an interconnection film on the insulating film and connected to the conductive film filled in the third hole.
In a method of manufacturing a semiconductor device according to the still further aspect of the present invention, the first film is removed by etching using the conductive film in the third hole as a mask. Therefore, the stepped portion can be reduced in the film formed on the insulating film at a subsequent process. Also, an underlying interconnection layer if present beneath the third hole will not be damaged because the third hole is filled with a conductive film.
In a method of manufacturing a semiconductor device, according to yet a further aspect of the present invention, the first film is of a conductive member and includes the steps of, after the step of forming the third hole, forming a conductive film on the first film so as to fill the third hole with the conductive film, exposing the first film by etching the conductive film and leaving the conductive film in the third hole so as to be in contact with the first film, and forming an interconnection film by patterning the exposed first film.
In a method of manufacturing a semiconductor device according to the yet further aspect of the present invention, the conductive film is etched leaving the conductive film in the third-hole to expose the first film. The first film is the interconnection film. Because the first film itself becomes an interconnection film, a stepped portion can be reduced in the film formed on the insulating film at a subsequent process. Also, an underlying lower layer interconnection if present beneath the third hole will not be damaged by etching because the third hole is filled with a conductive film.
According to yet another aspect of the present invention, a method of manufacturing the semiconductor device, after formation of the third hole, includes the steps of forming an amorphous silicon film on the first film so as to fill the third hole with the amorphous silicon film, applying thermal oxidation to the amorphous silicon film, so that the amorphous silicon film on the first film becomes a silicon oxide film and the amorphous silicon film in the third hole becomes a polycrystalline silicon film, removing the silicon oxide film and then the first film by etching using the polycrystalline silicon film in the third hole as a mask, and forming an interconnection film on the insulation film and connected to the polycrystalline silicon film filled in the third hole.
In a method of manufacturing a semiconductor device according to the yet another aspect of the present invention, first the silicon oxide film, and then the first film are removed by etching using the polycrystalline silicon film in the third hole as a mask. Therefore, the stepped portion can be reduced in the film formed on the insulating film at a subsequent process. Also, an underlying interconnection layer if present beneath the third hole will not be damaged by etching because the third hole is filled with the polycrystalline silicon film.
A method of manufacturing a DRAM according to the present invention includes the steps of: forming a MOS transistor on the main surface of a semiconductor substrate having a pair of impurity regions implementing the source/drain region, forming an insulating film on the main surface of the semiconductor substrate to cover the MOS transistor, forming on the insulating film a first film of a material having an under-etching characteristic different from that of the insulating film, forming on the first film a second film having a first hole above the impurity regions and of a material having an under-etching characteristic different from that of the first film, forming on the second film including a sidewall of the first hole a third film of a material having an under-etching characteristic identical to that of the second film, forming a sidewall layer at the sidewall of the first hole by etching anisotropically the third film, forming a second hole exposing the surface of the insulating film and having a diameter smaller than that of the first hole by etching anisotropically the first film using the second film and the sidewall layer as a mask, forming a third hole in the insulating film communicating with the second hole and exposing the impurity region by etching anisotropically the insulating film using the first film as a mask and removing the second film and the sidewall layer, forming a storage node on the insulating film connected to the impurity region via the third hole, forming a capacitor dielectric film on the storage node, and forming a cell plate on the capacitor dielectric film.
According to a preferable aspect of a method of manufacturing a semiconductor memory device of the present invention, the first film is formed of a conductive member, and the step of forming a storage node includes the steps of forming a conductive film on the first film and connected to the impurity region via the second and third holes, and forming a storage node of a layered structure of a first film and a conductive film by patterning the first film and the conductive film.
According to another preferable aspect of a semiconductor memory device according to the present invention, the storage node includes a first portion and a second portion, wherein the first portion extends over the upper surface of the insulating film so as to surround the circumference of the hole, and the second portion extends in contact with the upper face of the first portion and is connected to the impurity region via the hole.
According to one aspect of the present invention, a second film having a first hole is formed on a first film. The first hole is formed by photolithography or the like. Therefore, the diameter of the first hole cannot be made smaller than the minimum dimension can that be formed by photolithography. However, by forming a sidewall layer at the sidewall of the first hole, the diameter of the hole can be made smaller than the minimum dimension allowed by photolithography by the width of the sidewall layer. By applying an etching process using the second film and the sidewall layer of such a hole diameter as a mask, second and third holes can be formed in self-alignment in the first film and the insulating layer. The second and third holes can be formed having a diameter smaller than the minimum dimension that can be formed by photolithography. Therefore, under the same design rule, an opening can be formed in a smaller space, and the overlay margin can be increased in the patterning of photolithography.
According to a preferable aspect of a semiconductor memory device of the present invention formed by the above manufacturing method, the hole formed in the insulating film has an opening diameter greater than the minimum dimension that can be formed by photolithography. Therefore, the overlay margin between word lines are increased by the reduced dimension of the opening diameter even if a hole is formed between word lines. Thus, the pitch between word lines can be reduced to improve the integration density of memory cells and the like.
According to another preferable aspect of manufacturing a semiconductor memory device of the present invention, the step of forming a storage node includes the steps of forming a resist on the first film so that the third hole is filled with the resist, etching the resist leaving the resist in the third hole to expose the first film, etching away the first film using the resist in the third hole as a mask, removing the resist, and forming a storage node on the insulating film and connected to the impurity region via the third hole.
According to a preferable aspect of manufacturing a semiconductor memory device of the present invention, the first film is removed by etching using the resist in the third hole as a mask. Therefore, a stepped portion in the film formed on the insulating film at a subsequent step can be reduced. Furthermore, the impurity region at the bottom of the third hole is not damaged by the etching step of the first film since the third hole is filled with a resist.
According to another preferable aspect of manufacturing a semiconductor memory device of the present invention, the step of forming a storage node includes the steps of forming a conductive film so as to fill the third hole and on the first film to provide contact with the impurity region via the third hole, and etching the conductive film and the first film leaving the conductive film formed in the third hole, and forming a storage node on the insulating film in contact with the conductive film formed in the third hole.
According to a further preferable aspect of manufacturing a semiconductor memory device of the present invention, the first film is removed by etching using the conductive film in the third hole as a mask. Therefore, the stepped portion in the film formed on the insulating film at a subsequent step can be reduced. Because the third hole is filled with a conductive film, the impurity region at the bottom of the third hole will not be damaged by the etching process of the first film.
According to still another preferable aspect of manufacturing a semiconductor memory device of the present invention, the first film is formed of a conductive member, and the step of forming a storage node includes the steps of forming a conductive film so as to fill the third hole and on the first film to be connected to the impurity region via the third hole, etching the conductive film leaving the conductive film in the third hole to expose the first film, and patterning the first film to form a storage node.
According to another preferable aspect of manufacturing a semiconductor memory device of the present invention, the conductive film is removed by etching to expose the surface of the first film, leaving the conductive film only in the third hole. The first film serves as the interconnection film. Therefore, a stepped portion in a film formed on the insulating film at a subsequent step can be reduced. Because the third hole is filled with a conductive film, the impurity region at the bottom of the third hole will not be damaged by the etching process of the conductive film.
According to another preferable aspect of manufacturing a semiconductor memory device of the present invention, the step of forming a storage node includes the steps of forming an amorphous silicon film filling the third hole and on the first film to be connected to the impurity region via the third hole, thermal oxidizing the amorphous silicon film to change the amorphous silicon film on the first film to a silicon oxide film and the amorphous silicon film in the third hole to a polycrystalline silicon film, etching the silicon oxide film and then the first film using the polycrystalline silicon film in the third hole as a mask, and forming a storage node in contact with the polycrystalline silicon film in the third hole on the insulating film.
According to another preferable aspect of manufacturing a semiconductor memory device of the present invention, the silicon oxide film, and then the first film are removed by etching using the polycrystalline silicon film in the third hole as a mask. Therefore, a stepped portion in a film formed on the insulating film at a subsequent step can be reduced. Because the third hole is filled with a polycrystalline silicon film, the impurity region at the bottom of the third hole will not be damaged by the above-described etching step.
According to another aspect of manufacturing a semiconductor memory device of the present invention, the manufacturing step includes the steps of: forming a MOS transistor at the main surface of a semiconductor substrate having a pair of impurity regions which become the source/drain region; forming an insulating film on the main surface of the semiconductor substrate so as to cover the MOS transistor; forming a first conductive film of a material having an under-etching characteristic different from that of the insulating film, and then a first covering film of a material having an under-etching characteristic different from that of the first conductive film as stacked layers, followed by forming a first hole in the first conductive film and the first covering film; forming a second conductive film on the sidewall of the first hole and on the first covering film and of a material having an under-etching characteristic different from that of the first covering film; forming a sidewall layer on the sidewall of the first hole in contact with the first conductive film by etching anisotropically the second conductive film; etching anisotropically the insulating film using the sidewall layer as a mask to expose the impurity region in the insulating film to form a second hole having a diameter smaller than that of the first hole, and removing the covering film; forming a third conductive film so as to be in contact with the surface of the first conductive film and the sidewall layer, and connected to the impurity region via the second hole; forming a capacitor dielectric film so as to cover the surface of the storage node having the first conductive film, the sidewall layer, and the third conductive film, and forming a cell plate on the capacitor dielectric film.
According to a preferable aspect of manufacturing a semiconductor memory device of the present invention, the sidewall layer is formed of amorphous silicon.
According to another preferable aspect of a semiconductor memory device of the present invention, the storage node includes a first portion, a second portion, and the third portion, wherein the first portion is formed at a first level of height on the surface of the insulating film so as to surround the circumference of the hole. The second portion is formed at a second level of height lower than the first level of height on the upper face of the insulating film in contact with the lower end of the first portion and surrounding the first portion. The third portion extends in contact with the upper faces of the first and second portions, and is connected to the impurity region via the hole.
According to another aspect of manufacturing a semiconductor memory device of the present invention, the first hole is formed in the first conductive film and the first covering film. The first hole is formed by a photolithographic step. Therefore, the opening diameter of the first hole cannot be made smaller than the minimum dimension that can be formed by photolithographic technique. However, by forming a sidewall layer on the sidewall of the first hole, the opening diameter can be made smaller by the width of the sidewall layer than the minimum dimension allowed by photolithography. By applying an etching process using the first conductive film and the sidewall layer having such an opening diameter as a mask, the second hole can be formed in self-alignment in the insulating film. The second hole can be formed having an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique. Therefore, an opening can be formed in a smaller area under the same design rule, and the overlay margin in patterning by photolithographic technique can be increased.
According to another preferable aspect of a semiconductor memory device of the present invention formed by the above-described manufacturing method, the first portion of the lower electrode layer is formed in the inside portion of the second portion, and is upwards perpendicular to the main surface of the semiconductor substrate and higher than the surface of the second portion. More specifically, the lower electrode layer has a portion protruding upwards vertically in the inside portion. Therefore, the surface area of the lower electrode layer is increased by the portion protruding vertically upwards in comparison with a conventional capacitor formed of a relatively planar configuration. Therefore, the electrode opposing area between the upper electrode layer and the lower electrode layer can be increased to improve the capacitance. Even if the planar area of the capacitor is reduced, there is hardly no reduction in the surface area of the upward protruding portion. This means that the capacitance of a capacitor can be increased and ensured by controlling the surface area of the portion protruding upwards and vertically in the event of increasing the integration density.
Furthermore, even in a general cylindrical type capacitor, this protruding portion of the inside portion is applied, so that the surface area is increased by the portion extending upwards and vertically in the inside region. Thus, the electrode opposing area of a capacitor can be increased and ensured within a range of a limited level of height.
Because the capacitance of a capacitor can be increased or ensured, unstable operation or reduction in reliability of the operation of a DRAM associated with increase in integration density can be prevented.
According to another aspect of a method of manufacturing a semiconductor memory device of the present invention, the manufacturing method includes the steps of: forming a MOS transistor having a pair of impurity region serving as source/drain regions at the main surface of a semiconductor substrate; forming a first insulating film at the main surface of the semiconductor substrate so as to cover the MOS transistor and having a planarized upper surface; forming a first conductive film on the upper surface of the first insulating film with a second insulating film of a predetermined thickness therebetween; forming a second conductive film on the first conductive film with a third insulating film having a predetermined thickness therebetween; forming a first covering film having a hole above the impurity region on the second conductive film; forming a second covering film on the sidewall of the first hole and on the first covering film; forming a sidewall layer on the sidewall of the first hole by etching anisotropically the second covering film; etching anisotropically the second conductive film with the first covering film and the sidewall layer as a mask to expose the surface of the third insulating film and forming a second hole having a diameter smaller than that of the first hole; etching anisotropically the third insulating film, the first conductive film, the second insulating film, and then the first insulating film to form a third hole communicating with the second hole and exposing the impurity region, and removing the first covering film and sidewall layer; forming a third conductive layer so as to be in contact with the upper surface of the second conductive film and the first conductive film, and connected to the impurity region via the second and third holes; patterning the first, second and third conductive films to form a storage node; removing the second and third insulating films; forming a capacitor dielectric film so as to cover the surface of storage node; and forming a cell plate on the capacitor dielectric film.
According to another preferable aspect of a semiconductor memory device of the present invention, the insulating film has a planarized surface, and the storage node has a first portion, a second portion, and a third portion. The first portion extends in the direction along the upper surface of the insulating film with a predetermined distance from the upper surface thereof. The second portion extends in a direction along the upper surface of the insulating film above the first portion with a predetermined distance thereto. The third portion extends in contact with the upper face of the second portion, contacts the first portion, and is connected to the impurity region via the hole.
According to another aspect of a method of manufacturing a semiconductor memory device of the present invention, a first covering film having a first hole is formed on a second conductive film. The first hole is formed by photolithography, for example. Therefore, the opening diameter of the first hole cannot be made smaller than the minimum dimension that can be formed by photolithography. However, by forming a sidewall layer at the sidewall of the first hole, the opening diameter thereof can be made smaller by the width of the sidewall layer than the minimum dimension that can be formed by photolithography. By applying etching using the first covering film having such opening diameter and a sidewall layer as a mask, a second hole can be formed in self-alignment. The second hole can be formed having an opening diameter smaller than the minimum dimension that can be formed by photolithography. Thus, under the same design rule, a hole can be formed in a smaller space, and the overlay margin can be increased in patterning by photolithographic technique.
The first conductive film is formed on the first insulating film having a planarized surface with a second insulating film of a predetermined thickness therebetween. Therefore, there is no stepped portion in the layer underlying the first conductive film. Therefore, residue of the first conductive film will not remain at the sidewall of a stepped portion of the underlying layer in the step of forming a lower electrode layer by selectively etching away the first, second and third conductive films. Therefore, lower electrode layers will not be connected to each other by residues between a plurality of capacitors. Therefore, selective data storing and erasing can be carried out reliably between each memory cell.
According to a further aspect of a method of manufacturing a semiconductor memory device including a MOS transistor having a pair of impurity regions which become the source/drain regions, and a capacitor having a storage node, wherein the impurity region and the storage node are electrically connected via a first hole formed in an insulating film covering the MOS transistor, the manufacturing method includes the steps of forming on the insulating film a first film having a second hole above the impurity region, forming a second film all over the inside wall of the second hole and the surface of the first film, etching anisotropically the second film to form a sidewall layer on the sidewall of the second hole, etching anisotropically the insulating film with the first film and the sidewall layer as a mask to expose partially a surface of the impurity region and forming in the insulating film a first hole having a diameter smaller than that of the second hole.
According to an aspect of the present invention, a semiconductor memory device includes a semiconductor substrate having a main surface, a MOS transistor having a pair of impurity regions which become the source/drain regions on the main surface of the semiconductor substrate, an insulating film covering the MOS transistor and having a hole reaching the impurity region, a storage node formed on the insulating film so as to be connected to the impurity region via the hole, a capacitor dielectric covering the storage node, and a cell plate formed on the capacitor dielectric film. The hole formed in the insulating film has an opening diameter smaller than the minimum dimension that can be formed by photolithographic technique. The storage node has a portion extending along the direction on the surface of the insulating film. The extending portion extends in this direction stacked by at least two layers.
According to a preferable aspect of a semiconductor memory device of the present invention, the cell plate extends within the region of the hole, and is opposed to the storage node in the region of the hole with a capacitor dielectric film therebetween.
According to a method of manufacturing a semiconductor memory device summarizing the 3 above-described aspects of the present invention, a first film having a second hole is formed on an insulating film. This second hole is formed by a process of photolithography, for example. Therefore, the opening diameter of the second hole cannot be made smaller than the minimum dimension that can be formed by photolithography. However, by forming a sidewall layer at the sidewall of the first hole, the opening diameter thereof can be made smaller than the minimum dimension that can be formed by photolithography by the widths of the sidewall layer. By carrying out an etching step using the first film having this opening diameter and the sidewall layer as a mask, a first hole can be formed in the insulating film by self-alignment. The first hole can be formed with an opening diameter smaller than the minimum dimension that can be formed by photolithography. Therefore, in the same design rule, the opening can be formed in a smaller space, and the overlay margin is increased in patterning by photolithographic technique.
According to an aspect of a semiconductor memory device of the present invention formed by the above-described manufacturing method, the hole formed in the insulating film has an opening diameter smaller than the minimum dimension that can be formed by photolithography. Therefore, even when a hole is formed between word lines, the overlay margin between the hole and word line is increased by the distance of the reduced dimension of the opening diameter. Therefore, the pitch between word lines can be reduced to improve the integration density of a memory cell.